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White Electronic Designs
32MB to 4GB Flash Card
FEATURES
ATA compatibility Supports 3 variations of mode access * I/O Card Mode * Memory Card Mode * True- IDE Mode +5.5V / +3.0V single power supply. Internal Error Correction Logic * Data Interleave to 2 for each 256 Bytes. * Error Correction of 1 Byte random error per 128 Bytes of data. * Automatic on-the-fly, in-buffer error correction. Compatible with all PC Card Service and Socket Service. Integrated PC Card attribute memory of 256 Bytes(CIS). 4 PC Card function register support. Supports Host-side Write Protect. Automatic wake up from power-down on host reset or command write. Sector data transfers without microprocessor intervention. Operation Environment * Temperature -- 0C ~ 65C * Humidity -- 8% ~ 95%
WED7PXXXATA80XXC25
DESCRIPTION
The WED7PXXXATA80XXC25 series ATA card is an ATA interface flash memory card based on flash technology. The ATA card is constructed with a flash disk controller chip and NAND-type flash memory device. Operates from a single 5-Volt or 3.3-Volt power source. The card is available in ATA type-2 form factor from 32MB to 4GB unformatted capacity. Being able to emulate IDE hard disk drives, WEDC's ATA card is a perfect choice for solid-state mass-storage in industrial applications.
* This product is subject to change without notice.
PRODUCT TYPES
Card Density 32MB 64MB 128MB 256MB 512MB 1024MB 2048MB 4096MB
xx = Housing 03 = WEDC logo 04 = No logo
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
Model No. 7P032ATA80xxC25 7P064ATA80xxC25 7P128ATA80xxC25 7P256ATA80xxC25 7P512ATA80xxC25 7P1G0ATA80xxC25 7P2G0ATA80xxC25 7P4G0ATA80xxC25
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BLOCK DIAGRAM
WED7PXXXATA80XXC25
D0 to D15 BVD2/1SPKR/DASP# A0 to A10 CE1#, CE2# OE#, ATASEL# WE# IORD# IOWR# REG# RESET/RESET# CSEL# RDY/BSY#/IREQ#/INTRQ WP/IOIS16# INPACK# BVD1/STSCHG#/PDIAG# WAIT#/IORDY
Data Bus FAD [7:0]/FBD[7:0] Control Signal FCE/7..01 Controller Flash Memory
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
HOST INTERFACE
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WED7PXXXATA80XXC25
PIN ASSIGNMENTS AND PIN TYPE
Memory card mode Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Signal Name GND D3 D4 D5 D6 D7 CE1# A10 OE# N.C. A9 A8 N.C. N.C. WE# RDY/BSY Vcc N.C. N.C. N.C. N.C. A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND - - - - I I I I I I I I I/O I/O I/O O - I/O I/O I/O I/O I/O I I I - I I - - I O I/O I/O Card Mode Signal Name GND D3 D4 D5 D6 D7 CE1# A10 OE# N.C. A9 A8 N.C. N.C. WE# IREQ# Vcc N.C. N.C. N.C. N.C. A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND - - - - I I I I I I I I I/O I/O I/O O - I/O I/O I/O I/O I/O I I I - I I - - I O I/O True IDE Mode Signal Name GND D3 D4 D5 D6 D7 CE1# A10 ATASEL# N.C. A9 A8 N.C. N.C. WE# INTRQ Vcc N.C. N.C. N.C. N.C. A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16# GND - - - - I I I I I I I I I/O I/O I/O O - I/O I/O I/O I/O I/O I I I - I I - - I O I/O Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Memory card mode Signal Name GND CD1# D11 D12 D13 D14 D15 CE2# VS1 IORD# IOWR# NC NC NC NC NC Vcc NC NC NC NC CSEL# VS2 RESET Wait# INPACK# REG# BVD2 BVD1 D8 D9 D10 CD2# GND I/O - O I/O I/O I/O I/O I I O I I - - - - - - - - - - I O I O O I I/O I/O I/O I/O O O - I/O Card Mode Signal Name GND CD1# D11 D12 D13 D14 D15 CE2# VS1 IORD# IOWR# NC NC NC NC NC Vcc NC NC NC NC CSEL# VS2 RESET Wait# INPACK# REG# SPKR# STSCHG# D8 D9 D10 CD2# GND I/O - O I/O I/O I/O I/O I I O I I - - - - - - - - - - I O I O O I I/O I/O I/O I/O O O - True IDE Mode Signal Name GND CD1# D11 D12 D13 D14 D15 CE2# VS1 IORD# IOWR# NC NC NC NC NC Vcc NC NC NC NC CSEL# VS2 RESET# IORDY INPACK# REG# DASP PDIAG# D8 D9 D10 CD2# GND I/O - O I/O I/O I/O I/O I I O I I - - - - - - - - - - I O I O O I I/O I/O I/O I/O O O -
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ELECTRICAL SPECIFICATIONS
WED7PXXXATA80XXC25
ABSOLUTE MAXIMUM RATING
Symbol VCC VIN VOUT TSTG Parameter Power supply Input voltage Output voltage Storage temperature Rating -0.3 to 6.0 -0.3 to VCC+0.3 -0.3 to VCC+0.3 -40 to 125 Units V V V C
DC CHARACTERISTICS: I) Recommended Operating Conditions:
Symbol VCC VIN TOPR Parameter Power supply Input voltage Operating temperature Min. 3.0 0 -20 Max. 5.5 VCC 65 Units V V C
II) General DC Characteristics:
Symbol IIL IIH IOZ CIN COUT CBID Parameter Input low current Input high current Tri-state leakage current Input capacitance Output capacitance Bi-direction capacitance Conditions no pull up/down no pull up/down Min -1 -1 -10 4 4 4 Typ Max 1 1 10 pF pF pF Units A A A
III) DC Electrical Characteristics:
Symbol VIL VIH VIL VIH VOL VOH RI Parameter Input low voltage Input high voltage Schmitt input low voltage Schmitt input high voltage Output low voltage Output high voltage Input pull up/down resistance Min 0.7VCC 1.22 2.08 2.3 75 0.4 1 Typ Max 0.3VCC Units V V V V V V k
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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AC CHARACTERISTICS:
WED7PXXXATA80XXC25
Attribute Memory Read Timing Specification
Attribute Memory access time is defined as 300ns. Detailed timing specs are shown in Table below. Speed Version Item Read Cycle Time Address Access Time Card Enable Access Time Output Enable Access Time Output Disable Time from CE Output Disable Time from OE Address Setup Time Output Enable Time from CE Output Enable Time from OE Data Valid from Address Change Symbol tc(R) ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) tsu(A) ten(CE) ten(OE) tv(A) IEEE Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAVGL tELQNZ tGLQNZ tAXQX Min ns. 300 300 ns Max ns. 300 300 150 100 100 30 5 5 0
Note: All times are in nanoseconds. The CE# signal or both the OE# signal and the WE# signal must be de-asserted between consecutive cycle operations.
Configuration Register (Attribute Memory) Write Timing Specification
The Card Configuration write access time is defined as 250ns. Detailed timing specifications are shown in Table below. Speed Version Item Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Data Setup Time for WE Data Hold Time
Note: All times are in nanoseconds.
250 ns Symbol tc(W) tw(WE) tsu(A) trec(WE) tsu(D-WEH) th(D) IEEE Symbol tAVAV tWLWH tAVWL tWMAX tDVWH tWMDX Min ns 250 150 30 30 80 30 Max ns
Common Memory Read Timing Specification
Item Output Enable Access Time Output Disable Time from OE Address Setup Time Address Hold Time CE Setup before OE CE Hold following OE Wait Delay Falling from OE Data Setup for Wait Release Wait Width Time Symbol ta(OE) tdis(OE) tsu(A) th(A) tsu(CE) th(CE) tv(WT-OE) tv(WT) tw(WT) IEEE Symbol tGLQV tGHQZ tAVGL tGHAX tELGL tGHEH tGLWTV tQVWTH tWTLWTH Min ns. Max ns. 125 100
30 20 0 20 35 0 350 (3000 for CF+)
Note: The maximum load on -WAIT# is 1 LSTTL with 50pF total load. All times are in nanoseconds. The WAIT# signal may be ignored if the OE# cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12ps but is intentionally less in this specification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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AC CHARACTERISTICS (cont'd):
WED7PXXXATA80XXC25
I/O Input (Read) Timing Specification
Item Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD REG Setup before IORD REG Hold following IORD INPACK Delay Falling from IORD INPACK Delay Rising from IORD IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Wait Delay Falling from IORD Data Delay from Wait Rising Wait Width Time Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tsuREG(IORD) thREG(IORD) tdfINPACK(IORD) tdrINPACK(IORD) tdfIOIS16(ADR) tdrIOIS16(ADR) tdWT(IORD) td(WT) tw(WT) IEEE Symbol tIGLQV tIGHQX tIGLIGH tAVIGL tIGHAX tELIGL tIGHEH tRGLIGL tIGHRGH tIGLIAL tIGHIAH tAVISL tAVISH tIGLWTL tWTHQV tWTLWTH Min ns. 0 165 70 20 5 20 5 0 0 Max ns. 100
45 45 35 35 35 0 350 (3000 for CF+)
Note: Maximum load on WAIT#, INPACK# and I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is Onsec, but minimum IORD# width must still be met. Wait Width time meets PCMCIA specification of 12ps but is intentionally less in this spec.
I/O Output (Write) Timing Specification
Item Data Setup before IOWR Data Hold following IOWR IOWR Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR CE Hold following IOWR REG Setup before IOWR REG Hold following IOWR IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address Wait Delay Falling from IOWR IOWR high from Wait high Wait Width Time Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tsuREG(IOWR) thREG(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) tdWT(IOWR) tdrIOWR(WT) tw(WT) IEEE Symbol tDVIWH tIWHDX tIWLIWH tAVIWL tIWHAX tELIWL tIWHEH tRGLIWL tIWHRGH tAVISL tAVISH tIWLWTL tWTJIWH tWTLWTH Min ns. 60 30 165 70 20 5 20 5 0 Max ns.
35 35 35 0 350 (3000for CF+)
Note: The maximum load on WAIT#, INPACK#, and I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IOWR# high is Onsec, but minimum IOWR# width must still be met. The Wait Width time meets the PCMCIA specification of 12ps but is intentionally less in this specification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
AC CHARACTERISTICS (cont'd):
WED7PXXXATA80XXC25
True IDE Mode I/O Input (Read) Timing Specification
Item Data Delay after IORD Data Hold following IORD IORD Width Time Address Setup before IORD Address Hold following IORD CE Setup before IORD CE Hold following IORD I0IS16 Delay Falling from Address I0IS16 Delay Rising from Address Symbol td(IORD) th(IORD) tw(IORD) tsuA(IORD) thA(IORD) tsuCE(IORD) thCE(IORD) tdfIOIS16(ADR) tdrIOIS16(ADR) IEEE Symbol tIGLQV tIGHQX tIGLIGH tAVIGL tIGHAX tELIGL tIGHEH tAVISL tAVISH Min ns. 0 165 70 20 5 20 35 35 Max ns. 100
Note: The maximum load on I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is 0 nsec, but minimum IORD# width must still be met.
True IDE Mode I/O Output (Write) Timing Specification
Item Data Setup before IOWR Data Hold following IOWR IOWR Width Time Address Setup before IOWR Address Hold following IOWR CE Setup before IOWR CE Hold following IOWR I0IS16 Delay Falling from Address I0IS16 Delay Rising from Address Symbol tsu(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tdfIOIS16(ADR) tdrIOIS16(ADR) IEEE Symbol tDVIWH tIWHDX tIWLIWH tAVIWL tIWHAX tELIWL tIWHEH tAVISL tAVISH Min ns. 60 30 165 70 20 5 20 Max ns.
35 35
Note: The maximum load on I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IOWR# high is 0 nsec, but minimum IOWR# width must still be met.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE DIMENSIONS
WED7PXXXATA80XXC25
Type II
1.6mm 0.05 (0.063") 85.6mm 0.20 (3.370") 3.0mm MIN (0.118")
1.0mm 0.05 (0.039")
Substrate area
54.0mm 0.10 (2.126")
1.0mm 0.05 (0.039")
10.0mm MIN (0.400") 5.0mm T1 (0.197")
Interconnect area
3.3mm 0.10 (0.129")
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WED7PXXXATA80XXC25
PART NUMBERING GUIDE
WED 7P xxx ATA 80 xx C 25
WEDC Flash Memory Size ATA Flash Commercial Flash Housing: 03 = WEDC Logo 04 = Blank Housing Commercial Temp Speed
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
32MB to 4GB Flash Card
WED7PXXXATA80XXC25
Revision History Rev #
Rev 0
History
Initial Release
Release Date
March 2005
Status
Final
Rev 1
1.1 Added "ED" to part marking
July 2005
Final
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 1 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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